Electronic components are typically mounted on circuit panels consisting of multiple-layered dielectric sheets interspersed with conductors and vias arranged in a manner to properly connect surface-mounted devices. The electronic components that are generally mounted to circuit panels include discrete components, such as resistors and capacitors, and integrated circuits, with numerous sub-circuits embedded into a single semiconductor chip. Semiconductor chips are generally mounted onto chip carriers or mounting substrates which are then packaged before being mounted to the circuit panel with proper interconnecting leads. Circuit panels are generally formed of polymeric materials and chip carriers are generally made of ceramics or plastic. Semiconductor chips can also be mounted and connected directly to the circuit panel in a "hybrid circuit" configuration.
Semiconductor chips are commonly connected to electrically conductive traces on mounting substrates by various methods such as: wire bonding, tape automated bonding, and flip-chip bonding. In wire bonding, the chip is positioned on a substrate and individual wires are connected between the electrical contacts on the chip and pads on the substrate. In tape automated bonding, a flexible dielectric tape with a prefabricated array of cantilever leads thereon is positioned over the chip and the substrate. The individual leads are bonded to contacts on the chip. The leads are also connected to pads on the substrate. In both wire bonding and conventional tape automated bonding, the pads on the substrate are arranged outside of the area covered by the chip, so that the wires or leads fan out from the chip to the surrounding pads. The area covered by the subassembly as a whole is considerably larger than the area covered by the chip. Because the speed with which a microelectronic assembly can operate is inversely related to its size, this presents a serious drawback. Moreover, the wire bonding and tape automated bonding approaches are generally most workable with chips having contacts disposed in rows extending along the edges of the chip. They generally do not lend themselves to use with chips having contacts disposed in an area array, i.e., a gridlike pattern covering all or a substantial portion of the chip front surface.
In the flip-chip mounting technique, the contact bearing top surface of the chip faces towards the substrate. Each contact on the chip is joined by a solder bond to the corresponding pad on the substrate, as by positioning solder balls on the substrate or chip, juxtaposing the chip with the substrate in the front-face-down orientation and momentarily melting or reflowing the solder. The flip-chip technique yields a compact assembly which occupies a substrate area no larger than the area on the chip itself. However, flip-chip assemblies suffer from significant problems with stress caused by differential thermal expansion and contraction. The solder bonds between the chip contacts and substrate are substantially rigid. Changes in the size of the chip and of the substrate due to thermal expansion and contraction in service create substantial stresses in these rigid bonds, which, in turn, can lead to fatigue failure of the bonds.
Numerous attempts have been made to address the foregoing problems, and are described in U.S. Pat. Nos. 5,148,265; 5,148,266; 5,258,330; 5,282,312; 5,346,861; 5,347,159; 5,367,764; 5,398,863; 5,414,298; 5,455,390; 5,477,611; 5,489,749; 5,491,302; 5,518,964; 5,525,545; and 5,536,909. Exemplary embodiments of the structures disclosed in these patents incorporate flexible, sheet-like structures referred to as "interposers" or "chip carriers". The preferred chip carriers have a plurality of terminals disposed on a flexible, sheet-like top layer. In use, the interposer is disposed on the front or contact bearing surface of the chip with the terminals facing upwardly, away from the chip. The terminals are then connected to the contacts of the chip. This connection is made by bonding prefabricated leads on the interposer to the chip contacts, using a tool engaged with the lead. The completed assembly is then connected to a substrate, as by bonding the terminals of the chip carrier to the substrate. Because the leads and the dielectric layer of the chip carrier are flexible, the terminals on the chip carrier can move relative to the contacts on the chip without imposing significant stresses on the bonds between the leads and the chip, or on the bonds between the terminals and the substrate. Thus, the assembly can compensate for thermal effects. Moreover, the assembly includes a compliant layer disposed between the terminals on the chip carrier and the face of the chip itself as, for example, an elastomeric layer incorporated in the chip carrier and disposed between the dielectric layer of the chip carrier and the chip. Such a compliant structure permits displacement of the individual terminals independently of the chip.
Despite these and other advances in the art, it would be desirable to provide further improvements in semiconductor chip assemblies, components for these assemblies, and methods for making the same. These improvements should help reduce the noise generated by the integrated circuit package, minimize the external wiring between the chip carrier and the circuit panel, and allow the economical incorporation of normally externally mounted passive devices such as signal-conditioning and inductive components into a chip package with approximately the same footprint as the integrated circuit itself.